Automatic test pattern generation scans of integrated circuits, both with and without test compression, typically require at least four pins connected to the integrated circuit with the following functions: one scan input pin, one scan output pin, one clock pin and one scan enable signal pin. However, low pin count integrated circuits such as, for example, contactless smartcard integrated circuit 100 shown in FIG. 1 typically only has a total of four pins: two pins 120, 121 for the antenna which also provides the clock and supplies power via the radio frequency field to analog module 140 and digital module 130, one input/output pin 124 which is dedicated for testing and one ground pin 128. Therefore, contactless smartcard integrated circuits are typically tested using functional testing. However, as digital module 130 of contactless smartcard integrated circuit 100 increases in complexity, functional testing is typically insufficient and a structural test using a scan chain approach typically provides better test coverage in less test time but is typically unavailable due to the pin requirement. Additionally, allowing direct scan chain access on secure integrated circuits compromises security by allowing access to internal register values of the integrated circuit.